1. Field of the Invention
The present invention relates to a technique for reducing consumption power in a semiconductor static RAM of a clock-synchronized type.
2. Description of the Background Art
FIG. 7 is a circuitry diagram showing a portion of a semiconductor static RAM (hereinafter "SRAM")of a clock-synchronized type, having a conventional structure. For simplicity, FIG. 7 shows only two word lines WORD0 and WORD 1 and two bit line pairs (BIT00, BIT01) and (BITI0, BIT11). Further, also for simplicity, FIG. 7 shows only two memory cells for each one of the word lines and the bit line pairs, i.e., MC00, MC01, MC10 and MC11, although a number of memory cells are disposed for each one of the word lines and the bit line pairs in reality.
Each memory cell MCij (i=0, 1; j=0, 1) is formed by six transistors, namely, PMOS transistors PMij0, PMij1 which serve as load transistors, NMOS transistors NAij0, NAij1 which serve as access transistors, NMOS transistors NDij0, NDij1 which serve as drive transistors. In FIG. 7, reference characters are allotted to the transistors which are included in the memory cell MC00 alone, for simplicity of illustration.
A power source potential VDD is supplied to sources of the PMOS transistors PMij0, PMij1, while a ground potential GND is supplied to sources of the NMOS transistors NDij0, NDij1.
At a node Aij, a gate of the load transistor PMij0, a gate of the drive transistor NDij0, a drain of the load transistor PMij1, and a drain of the drive transistor NDij1 are connected in common. At a node Bij, a gate of the load transistor PMij1, a gate of the drive transistor NDij1, a drain of the load transistor PMij0, and a drain of the drive transistor NDij0 are connected in common.
Data are stored in the memory cell MCij when the nodes Aij and Bij receive mutually exclusive logic. The node Aij is connected to a bit line BITj0 through the access transistor NAij0, and the node Bij is connected to a bit line BITj1 through the access transistor NAij1.
FIG. 8 is a timing chart showing reading from the memory cell MC00 which is shown in FIG. 7. As herein defined, the "H" level is the power source potential VDD, and the "L" level is the ground potential GND.
The reading operation starts at a leading edge of a clock signal CLK. Delayed from the leading edge of the clock signal CLK by a time tw which is necessary for a column address signal to be decoded, an original column select signal Y0 rises. An inverted logical product of the column select signal Y0 and the clock signal CLK is created at an NAND gate G0, whereby a column select signal YB0 falls. This conducts PMOS transistors, or gate transistors, PG00 and PG01, and allows the bit lines BIT00 and BIT01 of one bit line pair to be connected to a sense amplifier SA (bit line select state).
Further, delayed from the leading edge of the clock signal CLK by the time tw which is necessary for the column address signal to be decoded, a potential at the word line WORD0 rises (i.e., the word line WORD0 is selected).
A precharge signal PRC stays at the low level until a word line is selected. When a PMOS transistor PRij to which the precharge signal PRC is supplied is conducted, each bit line is precharged to the power source potential VDD.
Now, assuming that the "H" level is maintained at an node A00 and the "L" level is maintained at an node B00 in the memory cell MC00, drive transistors ND000 and ND001 remain conductive and non-conductive, respectively.
When the word line WORD0 is selected (i.e., when a potential at the word line WORD0 rises), the precharge signal PRC rises and precharging is stopped. Meanwhile, a charge in the bit line BIT01 is discharged from an access transistor NA001 through the drive transistor ND000. Hence, the potential at the bit line BIT01 starts falling down from the "H" level to the "L" level. On the other hand, since an access transistor NA000 does not carry a current because the dive transistor ND001 is not conducting, a potential at the bit line BIT00 remains at "H" level.
The column select signal YB0 then switches to the low level, so that the gate transistors PG00 and PG01 are conducted. As a result, the sense amplifier SA detects a difference between the potentials on the bit lines BIT00 and BIT01 of one bit line pair, which in turn allows the data which are stored in the memory cell MC00 to be retrieved.
Following this, the word lines and the bit lines are switched to the non-conductive condition, in response to falling of the clock signal CLK. In addition, the precharge signal PRC falls and the PMOS transistors PRij initialize all bit line to the "H" level, thereby completing the reading operation.
Since precharging is performed on all bit lines, when a potential at the word line WORD0 is changed to the "H" level, a current flows from the access transistor NA0j1 to the drive transistor ND0j0 or from the access transistor NA0j0 to the drive transistor ND0j1 in each one of the memory cells MC0j.
However, to obtain data from the sense amplifier SA, it is necessary to select only one bit line pair, rather than selecting a plurality of bit lines. For instance, in the example described with reference to FIG. 8, the column select signal YB0 falls so as to obtain the data which are stored in the memory cell MC00 from the sense amplifier SA. A column select signal YB1 never falls at this stage. That is, a potential difference between the bit lines BIT10 and BIT11 is not detected.
Hence, a current which flows in such an occasion in the memory cell MC01 because of the access transistors and the drive transistors does not contribute to reading of data, and therefore, is not necessary. In other words, such a current which is not needed for a desired operation disadvantageously increases consumption of a current.
Such an unnecessary current increases as the number of columns (i.e., the number of the bit line pairs) which share the same one sense amplifier SA increases. For example, where a current of 0.1 mA flows during reading from one memory cell and the number of the columns which share the same sense amplifier is 64, although a current which is necessary for the reading operation is 0.1 mA, a current of 6.4 mA flows in reality.